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The pyVHDLParser Documentation

This is a token-stream based parser for VHDL-2008 creating a document object model (DOM).

Important

This package requires Python 3.8+, because it uses some of the latest Python feature for effective code writing:

Main Goals

  • Parsing

    • Slice an input document into tokens and text blocks which are categorized in groups for fast indexing

    • Preserve case, whitespace and comments

    • Recover on parsing errors

    • Good error reporting / throw exceptions

  • Fast Processing

    • Multi-pass parsing and analysis

    • Delay analysis if not needed for current pass

    • Link tokens and blocks for fast-forward scanning (triple helix)

  • Generic VHDL Language Model

    • Assemble a sourcecode document-object-model (Code-DOM)

    • Provide an API for code introspection

    • Provide an API for code modification / transformation

See chapter Project Goals for details.

Use Cases

See also

See chapter Use Cases for details.

Parsing Approach

  1. Slice an input document into tokens

  2. Assemble tokens to text blocks which are categorized

  3. Assemble text blocks for fast-forward scanning into groups (indexing)

  4. Translate groups into a sourcecode document-object-model (Code-DOM)

  5. Provide a generic VHDL language model

See also

See chapter Concepts for details.

Additional Aims

  • A VHDL domain for Sphinx

    • A autodoc plugin for the VHDL domain in Sphinx

  • VHDL plugins/extensions for style checkers supported by CI environments

  • Testing new VHDL language features beyond VHDL-2008/VHDL-2019

News

Nov. 2020 - Test cases

  • Added testcases for Tokenizer and block generation.

  • Added first testcases for pass 4 (Code-DOM)

  • Collect code and branch coverage.

  • Frontend.py → pyVHDLParser executable installed via pip

Dec. 2019 - Major reworks

  • Reworked and updated documentation.

  • Implemented a new test frontend.

Dec. 2018 - Minor updates

Fixed some NextToken linking problems.

Nov. 2017 - New features

Implemented new features like case statements.

20.09.2017 - Project started

Let’s create a new parser in Python to process VHDL code.

Contributors

License

This library is licensed under Apache License 2.0.


This document was generated on 10.Jun 2021 - 10:08.